ASIC Engineering Technical Leader

Company: Cisco Systems, Inc.
Location: San Jose
Posted on: January 25, 2025

Job Description:

This is an onsite role and will require working out of the Milpitas/San Jose office location. Application for this role is expected to close 2/28/2025Who We AreThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.Who You'll Work WithYou will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.What You'll Do

• Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.
• Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
• Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
• Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedule.
• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.Minimum Qualifications:
  • Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
  • Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Prior experience in hardware design specifications and verification plan/matrix, RTL & testbench implementations.
  • Prior experience on DFT quality sign off checklist and reviews for chip tape out, including test coverage, STA.
  • Prior experience with pre-silicon DFT implementation and verification flows, and post-silicon test bring up procedures.
  • Prior experience with verification skills including, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
  • Prior experience in Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687; Ability to analyze and root cause test failures on ATE.Preferred Qualifications:
    • Prior experience with DFT CAD development - Test Architecture, Methodology and Infrastructure.
    • Prior experience with Post silicon validation using DFT patterns.Why Cisco?#WeAreCisco , where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses.Message to applicants applying to work in the U.S. and/or Canada:When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits.Sign up to receive notifications of similar jobs
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Keywords: Cisco Systems, Inc., Cupertino , ASIC Engineering Technical Leader, Engineering , San Jose, California