Senior ASIC STA Engineer

Company: Cisco Systems, Inc.
Location: San Jose
Posted on: January 26, 2025

Job Description:

The application window is expected to close on: 02/24/2025 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact *This role expects you to be responsible for closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and STA, along with advising the Physical Design team on best practices. *Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. *Experience in generating timing constraints and performing quality checks such as setup, hold, transition, and noise. *Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery.*Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates *Proficient in synthesis constraints and using industry standard synthesis tools.
Minimum Qualifications*Bachelor's degree in electrical or computer engineering (or other equivalent field) with 7+ years of related work experience. *Prior experience using Synthesis Tools: Synopsys DC/DCG/FC. *Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus. *Prior experience with scripting such as TCL, Perl, or Python.
Preferred Qualifications*Master's degree in electrical or computer engineering (or other equivalent field) with 4+ years of related work experience. *Experience using: Synopsys PTPX/Tweaker/PrimeClosure *Experience using Formal Verification: Synopsys Formality and Cadence LEC. *Experience using Parasitic Extraction: Synopsys Star-RCXT, Cadence Quantus.
#WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!

Keywords: Cisco Systems, Inc., Cupertino , Senior ASIC STA Engineer, Engineering , San Jose, California